In digital logic systems utilizing a large number of boards or cards for mounting a plurality of integrated circuits, master clock signals are frequently generated by a common clock generator circuit. The clock pulses produced thereby are distributed throughout the logic system. These clock pulses provide timing signals at a particular time within the repetitive clock cycle provided by a master system clock. The clock pulses, however, may not be suitable for the purpose of controlling the operation of all the circuits on a given chip. Hence, a clock chopper may be required on the chip to produce from the system clock pulses input thereto a suitable set of on-chip clock pulses.
Clock chopper circuits are quite widely used in various applications. Generally, the circuits produce a pulse which has a shorter duration than the system clock pulses input thereto. Examples of such clock choppers are found in the IBM Technical Disclosure Bulletin Volume 29, No. 7, December 1986, pages 3148-3151 (Chan) and commonly owned U.S. Pat. No. 4,851,711 (Chan et al.).
Chan discloses a clock chopper circuit designed around complementary transistor switch (CTS) random access memories that offers relatively low complexity and minimal chip access penalty. In Chan, a master clock input is provided to a timing enable receiver which provides complementary inputs to a delay generator configured from a CTS memory cell. The time required to write the cell determines the width of the generated delayed pulse. The output of the delay generator is thereafter coupled by a level converter circuit to a gate receiver (OR) circuit, which ORs the master clock input signal with the delayed pulse to thereby produce the shortened output clock pulses. A drawback to the clock chopper disclosed in Chan is that the cycle time of the circuit is limited to being greater than the combined turn on (select) and turn off (restore or settling) time for the CTS memory cell, the turn on and turn off times being approximately equal. Accordingly, circuits of the type described in Chan are limited to applications where the cycle time is at least as long as the set and reset time of a CTS memory cell.
Chan et al. discloses an improvement to the clock chopper circuit of Chan utilizing an asymmetrical delay generator circuit. The Chan et al. delay generator circuit is based on a CTS memory cell which operates differently than the one described in Chan. In Chan et al., one half of the cell operates in saturation and controls the pulse width of the chopper while the other half of the CTS cell is not operated in saturation and controls the resetting of the chopper circuit. The delay pulse thereby generated is asymmetrical because the write time of the cell is longer than the read, or reset, time. The clock chopper circuit disclosed in Chan et al. can therefore chop higher input clock rates than that of Chan.
Chan and Chan et al. both disclose clock chopper circuits wherein a delay generator circuit is the primary contributor for determining the output pulse width and hence, the clock chopping function. The delay generator circuits in both references utilize the write and reset time of a CTS memory cell for establishing the actual delay. The cycle time for each circuit is limited to being greater than the turn on and turn off time for each cell. CTS type memory cells, however, have relatively slow restore or settling times when compared with current technology. Clock chopper circuits are required which operate faster than these devices.
Another drawback to the clock chopper disclosed in Chan et al. concerns the integration of Schottky Barrier Diodes SL, SS, and SR into the circuit, because the operating characteristics of these devices are difficult to control. The delay represented by these diodes alone is sometimes longer than the maximum delay allowable.
Chan and Chan et al. represent typical clock chopper circuits known in the prior art. A device which overcomes the aforementioned drawbacks of these circuits is therefore highly desirable.